{"id":67,"date":"2019-01-10T16:09:18","date_gmt":"2019-01-10T15:09:18","guid":{"rendered":"http:\/\/virtual-waves.com\/?page_id=67"},"modified":"2026-01-19T13:11:59","modified_gmt":"2026-01-19T12:11:59","slug":"services","status":"publish","type":"page","link":"https:\/\/virtual-waves.com\/index.php\/services\/","title":{"rendered":"SERVICES"},"content":{"rendered":"\t\t
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<\/p>\n

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We provide a wide range of services<\/h4>\n<\/div>\n<\/div>\n

Design of Mid-to-Highly Complex Embedded Systems: From software and firmware coding, to complex high-speed boards design.<\/p>\n

You can depend on us to develop reliable and cutting-edge solutions.<\/p>\n

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A complete HDL design LR 1-7 (IP free). Ported and validated on Altera(Arria 10, Stratix 10 SoC) and Xilinx (Kintex 7, UltraScale) FPGAs.<\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t

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A complete HDL and C++ design with the following functional splits: Split D, ID, IID, IU, O-RAN\/xRAN’s split 7-2. Allowing a packet-based communication between O-DU and O-RU. Design was validated on Xilinx UltraScale+MPSoC FPGA.<\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t

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This HDL + software design allows the bridging between eCPRI packets and CPRI hyperframes and vice-versa. When the CPRI core is instantiated as a Slave port (RE), the eCPRI timing will be recovered and transferred to the CPRI domain. Design was validated on Xilinx UltraScale+MPSoC FPGA.<\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t

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A complete HDL design (IP free) for connecting your high-speed ADCs and DACs using the jesd204B\/C subclass-1 protocols instead of complex PCB routing for parallel bus LVDS or LVCMOS signaling.<\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t

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A C++-11\/14 and Python high-level configuration interfaces that generate a complete HDL design (IP free) of Digital Up\/Down Converter (DUC\/DDC) blocks. The modules were validated on real LTE signals. Filter type selection is either CIC, FIR (Symmetric, Systolic, Interpolated, Poly-Phase, RAG, DA …) based on system requirements.<\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t

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Design, from the ground-up, a complete System On Module (SOM) boards + its software and firmware stacks for DSP processing on FPGA for 4G and 5G signals.<\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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\n\t\t\t\t\t\tFor confidentiality reasons, we do not disclose the names of our customers or the nature of the projects to which we have contributed. We work under Non-Disclosure Agreement (NDA) with our customers for sensitive information exchanges.\t\t\t\t\t<\/p>\n\t\t\t\t\n\t\t\t<\/div>\n\t\t\t\n\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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\n\t\t\t\t\t\t\n\t\t\t\t\t\t\tTraining Sessions\t\t\t\t\t\t<\/span>\n\t\t\t\t\t<\/h3>\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>\n\t\t\t\n\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t
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This 5-days<\/strong> training will allow current students, engineers and Linux enthusiasts to acquire the required practical skills and know-how to boot & configure the Linux kernel for an embedded system. This know-how can then be easily extended to use the same learned processes to embed Linux OS within other processor architectures and boards.<\/p>\n

The processor architecture that will be used in the training sessions will be either an ARM Cortex-A5 or a Quad Core Cortex-A35.<\/p>\n

<\/i> Embedded Linux kernel training outline<\/a><\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t

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This 5-days<\/strong> training will allow current students, engineers and embedded systems enthusiasts to take a deep-dive into real time operating system architecture and mastering the C-language best practices for embedded system. During the sessions we will learn how to develop & enrich the basic RTOS by adding several stacks and services (e.g., file system, TCP\/IP, IoT library, webserver).<\/p>\n

Practical labs will be held on an ARM Cortex-A5 processor using the FreeRTOS as an operating system.<\/p>\n

<\/i> Embedded RTOS C programming expert training outline<\/a><\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t

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This 5-days<\/strong> training will allow current students, engineers and telecom designers to have the required skills and know-how for implementing and running software defined 4G and 5G radio services on Linux PCs with some hardware acceleration boards (FPGA or GPU).<\/p>\n

Labs will focus on the 5G-NR implementation with FPGA processing acceleration.<\/p>\n

<\/i> Telecom 5G system designer training outline<\/a><\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t

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This 5-days<\/strong> training will allow current students, engineers and hardware designers to have the required skills and know-how for designing complex PCB boards.<\/p>\n

Practical labs will be held with Altium 18 Designer.<\/p>\n

<\/i> Hardware complex PCB designer training outline<\/a><\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t

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\n\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/i><\/span>\n\t\t\t\t\t\t\t\t<\/i><\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t\t\tEmbedded - Linux Device Drivers<\/a>\n\t\t\t\t\t<\/div>\n\n\t\t\t\t\t

This 5-days<\/strong> training will allow current students, engineers and Linux enthusiasts to acquire the required practical skills and know-how to integrate device drivers with other parts of the kernel and with user applications.<\/p>\n

The processor architecture that will be used in the training sessions will be either an ARM Cortex-A5 or a Quad Core Cortex-A35.<\/p>\n

<\/i> Embedded Linux device drivers training outline<\/a><\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t

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This 5-days<\/strong> training will allow current students, engineers and DSP designers to have the required skills and know-how for designing and implementing, on FPGA, complex DSP algorithms that are mainly used in 4G\/5G systems. The know-how and methodology acquired during the training will help easing the design of other DSP blocks.<\/p>\n

Practical labs will be held on a Xilinx UltraScale+MPSoC boards connected to high-speed ADC & DAC converters.<\/p>\n

<\/i> FPGA DSP designer training outline<\/a><\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t

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\n\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/i><\/span>\n\t\t\t\t\t\t\t\t<\/i><\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t\t\tFPGA - System Designer<\/a>\n\t\t\t\t\t<\/div>\n\n\t\t\t\t\t

This 5-days<\/strong> training will allow current students, engineers and firmware designers to have the required skills and know-how for designing and coding HDL modules for complex FPGA architectures. We will cover also FPGA design examples for Deep Learning applied to Artificial Intelligence (AI).<\/p>\n

Practical labs will be held on a Xilinx Zynq UltraScale+ MPSoC FPGA boards.<\/p>\n

<\/i> FPGA system designer training outline<\/a><\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t

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This 5-days<\/strong> training will allow current students, engineers and firmware designers to take a deep-dive into the VHDL language. We target to teach how to write high quality VHDL-2008 code that reflect the best practices in the industry. TestBenchs and functional verification methodologies will be based on the UVVM and OSVVM models.<\/p>\n

Practical labs will be held on PCs with Questa simulator installed.<\/p>\n

<\/i> FPGA VHDL expert training outline<\/a><\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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Need a training!<\/h2>For more information just fill out this form and we\u2019ll give you a call as soon as we can.<\/span> <\/div>\n
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